Many types of integrated circuit chips utilize wire bonding as a means connecting the integrated circuit chip to the next higher level of packaging, for example, for the chip connecting to a module. Wire bonding requires wire bond pads be placed on the periphery of the integrated circuit chip. Since wire bond pads are exposed to the ambient environment, sealing the edges of the wire bond pads is a requirement. Otherwise early failures and reliability problems can occur.
As integrated circuit chips have become smaller, feature (such as interconnect wire widths and spacing) sizes have been reduced and input/output (I/O) pin density has increased to increase productivity, but wire bond pads have not decreased in size or pitch (the center to center spacing of adjacent wire bond pads) proportionally to the decrease in chip and feature sizes. The industry has turned to other I/O pad types such as solder bump, that offer greater I/O density, though at a greater cost which reduces productivity.
Therefore, there is a need for a high density wire bond pad structure that offers increased I/O count without sacrificing reliability or impacting productivity.